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ISL62386
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input capacitor
RMS ripple current, normalized relative to output load current,
as a function of duty cycle and is adjusted for converter
efficiency. The normalized RMS ripple current calculation is
written as Equation 22:
off, the high-side MOSFET turns off with a V DS of
approximately V IN - V OUT , plus the spike across it. The
preferred low-side MOSFET emphasizes low r DS(ON) when
fully saturated to minimize conduction loss. It should be
noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For
D ? k
I C
IN
( RMS , NORMALIZED )
2
12
I MAX ? D ? ( 1 – D ) + --------------
= -----------------------------------------------------------------------
I MAX
(EQ. 22)
higher output, low input voltage solutions, a more balanced
MOSFET selection for high- and low-side devices may be
warranted.
P CON_LS ≈ I LOAD ? r DS ( ON ) _LS ? ( 1 – D )
Where:
- I MAX is the maximum continuous I LOAD of the converter
- k is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 24:
2
(EQ. 24)
For the high-side (HS) MOSFET, the conduction loss is
written as Equation 25:
the efficiency of the converter which is written as:
Equation 23.
P CON_HS = I LOAD
2
?
r DS ( ON ) _HS ? D
(EQ. 25)
V OUT
D = --------------------------
P SW_HS = ----------------------------------------------------------------- + -------------------------------------------------------------
(EQ. 23)
V IN ? EFF
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
For the high-side MOSFET, the switching loss is written as
Equation 26:
V IN ? I VALLEY ? t ON ? f SW V IN ? I PEAK ? t OFF ? f SW
2 2
(EQ. 26)
0.60
Where:
0.48
- I VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
0.36
0.24
0.12
k=1
k = 0.75
k = 0.5
k = 0.25
k=0
- I PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into
saturation
- t OFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 27:
Δ V BOOT
0
0
0.1
0.2
0.3
0.4 0.5 0.6
DUTY CYCLE
0.7
0.8
0.9
1.0
Q g
C BOOT = ------------------------
(EQ. 27)
FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET which has the
drain-source voltage clamped by its body diode during turn
17
Where:
- Q g is the total gate charge required to turn on the
high-side MOSFET
- Δ V BOOT , is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of
200mV. The calculated bootstrap capacitance is 0.125μF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22μF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
FN6831.0
February 4, 2009
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